Low loss interconnect structure for use in microelectronic circuits

ABSTRACT

A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

FIELD OF THE INVENTION

The invention relates generally to microelectronic circuits and, moreparticularly, to interconnect structures for use therein.

BACKGROUND OF THE INVENTION

Microelectronic devices generally include many on-die interconnects toprovide signal delivery and distribution functions for the circuitry.These interconnects are typically used to carry, for example, clocksignals, power signals, and/or data signals to various points on thedie. In the past, the loss within these on-die interconnects was not aprimary concern. Instead, the interconnects were designed to preventringing and other signal compromising effects. The loss within on-dieinterconnects, however, is now becoming a greater concern. For example,one low skew clocking strategy that is currently being considered foruse within microelectronic devices is salphasic clocking. Salphasicclocking uses standing waves on a transmission medium to distribute aclock signal in a relatively low skew manner. To generate standing wavesthat are adequate to support salphasic clocking, however, transmissionstructures having relatively low loss are typically required. For thisand other reasons, there is a need for low loss interconnect structuresthat can be implemented on-die within a microelectronic device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are a top view and a sectional side view, respectively, ofa conventional interleaved on-die interconnect structure;

FIGS. 3 and 4 are a top view and a sectional side view, respectively, ofa low loss on-die interconnect structure in accordance with oneembodiment of the present invention;

FIG. 5 is a block diagram illustrating the use of a low loss on-dieinterconnect structure as a point to point communication link within amicroelectronic device in accordance with one embodiment of the presentinvention;

FIG. 6 is a diagram illustrating a standing wave on a losslesstransmission line terminated in a short circuit;

FIG. 7 is a diagram illustrating a standing wave on a lossy transmissionline terminated in a short circuit; and

FIG. 8 is a block diagram illustrating the use of a low loss on-dieinterconnect structure within a salphasic clock grid to providesalphasic clock distribution within a microelectronic device inaccordance with one embodiment of the present invention.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that the variousembodiments of the invention, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein in connection with one embodiment may beimplemented within other embodiments without departing from the spiritand scope of the invention. In addition, it is to be understood that thelocation or arrangement of individual elements within each disclosedembodiment may be modified without departing from the spirit and scopeof the invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims, appropriately interpreted, alongwith the full range of equivalents to which the claims are entitled. Inthe drawings, like numerals refer to the same or similar functionalitythroughout the several views.

The present invention relates to a low loss interconnect structure thatcan be implemented on-die within a microelectronic device. Theinterconnect structure can be used to replace many of the variousinterconnects commonly implemented on-die, particularly those used inresonance applications. In clocking networks, for example, the structurecan be used to provide, point-to-point connections, tree structures,and/or various grid hierarchies. Because of its low loss, theinterconnect structure is particularly beneficial when used as part of asalphasic clock distribution network within a microelectronic circuit.As is well known, the use of low loss transmission structures insalphasic systems can result in significantly lower clock skews within asystem.

Clocking networks and other on-die signal distribution structures havetraditionally been characterized as simple resistance-capacitance (RC)networks. One goal when designing such networks, therefore, has been tominimize circuit inductance. One method to minimize inductance is toplace conductive signal return structures close to the signal lines toreduce the size of the effective inductive loop. This technique isenhanced by interleaving signal traces with return traces on the samemetal layer of the die. FIGS. 1 and 2 are a top view and a sectionalside view, respectively, of a conventional interleaved interconnectstructure 10 that incorporates these principles. As illustrated, theinterconnect structure 10 includes a plurality of signal traces 12 thatare interleaved on a common metal layer with a plurality of returntraces 14. A wide parallel return member 16 is located on a layer belowthe interleaved traces 12, 14. The return member 16 runs parallel to thesignal and return traces 12, 14 and has a width that is the same as orsimilar to the total width of the interleaved traces. Another wideparallel return trace (not shown) can also be provided above theinterleaved traces 12, 14 to further reduce series inductance. Thereturn traces 14 and the wide return member 16 can be, for example,power or ground structures within the microelectronic die. Often,further inductance reduction will be undertaken for an interconnect byincreasing the resistance and capacitance associated with the structure.Resistance can be increased significantly by decreasing the signalconductor width to less than twice the skin depth of the lines.Capacitance can be increased by adding additional interleaved conductorsto the interconnect 10. All of these techniques, however, serve toincrease the overall signal loss of the interconnect. As describedabove, future devices will require less signal loss on the individualinterconnects of the device.

FIGS. 3 and 4 are a top view and a sectional side view, respectively, ofa low loss interconnect structure 20 in accordance with one embodimentof the present invention. The low loss interconnect structure 20 can beimplemented, for example, on-die within a microelectronic device (e.g.,a microprocessor, a chip set, etc.). The interconnect structure 20includes first and second differential signal lines 22, 24 on a firstmetal layer to carry a differential signal within the device. Theinterconnect structure 20 may also include one or more orthogonal traces26, 28 on another metal layer to provide a possible return path forsignal components on the first and second differential signal lines 22,24. In a microelectronic die, wire directions typically alternate oneach successive metal layer. To implement the conventional interconnectstructure 10 of FIGS. 1 and 2, therefore, this convention must be brokento allow the wide return member 16 to be parallel with the interleavedsignal and return traces 12, 14. Using the interconnect structure 20 ofFIGS. 3 and 4, however, allows the convention to be followed by allowingorthogonal lines 26, 28 to be present on the adjacent metal layers. Theorthogonal lines 26, 28 can include, for example, signal or power lineswithin the microelectronic device. As will be discussed in greaterdetail, the orthogonal lines 26, 28 may also provide a return path forsignals propagating on the differential signal lines 22, 24.

The attenuation coefficient (α) of a transmission line can berepresented by the following equation:α=Re((R+jωL)(G+jωC))where R is the series resistance per unit length, L is the seriesinductance per unit length, G is the shunt conductance per unit length,and C is the shunt capacitance per unit length. In conceiving thepresent invention, it was appreciated that the loss of a transmissionline could be reduced significantly by decreasing R/L withoutsignificantly increasing C. In the interconnect structure 20 of FIGS. 3and 4, the orthogonal traces 26, 28 on the lower metal layer arecapacitively coupled to the differential signal traces 22, 24. However,because they are orthogonal to the signal traces 22, 24, the orthogonaltraces 26, 28 present a high impedance (e.g., high inductance) returnpath to signal components propagating on the differential signal traces22, 24. For this reason, the best return path for each differentialsignal trace 22, 24 is through the other differential signal trace24,22. As desired, this high inductance return path serves to decreasethe value of R/L. Further reduction in the value of R/L is achieved bymaking the signal traces 22, 24 relatively wide to reduce R within theinterconnect 20. In one design approach, a reasonable interline spacingis initially chosen for the differential signal traces 22, 24. Thewidths of the differential signal traces 22, 24 are then increased untilthe corresponding increase in capacitance begins to increase the loss ofthe interconnect 20. The spacing between the differential signal traces22,24 is then increased from the initial value until the additionaldecrease in loss due to the increase in inductance no longer justifiesthe increased area consumed by the interconnect 20. One or moreadditional design iterations may then be performed to further optimizethe widths and/or spacing of the traces 22, 24.

Because the interconnect 20 of FIGS. 3 and 4 is a differentialstructure, it is capable of rejecting common mode noise within amicroelectronic device. To support differential operation, the drivers,receivers, and repeaters (if any) used in connection with theinterconnect 20 should be differential structures. In oneimplementation, an interconnect using the inventive principles achieveda loss of 0.790 decibels per millimeter (dB/mm) and a phase constant of0.885 radians/mm at an operational frequency of 10 gigahertz (gHz). Incontrast, a conventional interconnect (e.g., interconnect 10 of FIG. 1)having similar dimensions and materials produces a loss of 1.867 dB/mmand a phase constant of 0.610 radians/mm at 10 gHz.

FIG. 5 is a block diagram illustrating the use of a low loss on-dieinterconnect structure 40 to provide a point to point connection withina microelectronic device in accordance with one embodiment of thepresent invention. As illustrated, a differential driver 42 associatedwith a first electrical component 44 (COMPONENT A) is coupled to a firstend of the interconnect 40 to provide a differential signal (e.g., aclock or data signal) to the interconnect 40 for transmission to asecond electrical component 48 (COMPONENT B). A differential receiver 46within the second electrical component 48 receives the differentialsignal from the interconnect 40 for use by circuitry within the secondcomponent 48. As shown, the interconnect 40 includes first and seconddifferential signal lines 50, 52 that are located on a common metallayer of the associated die. A pair of orthogonal traces 54, 56 arelocated on a different metal layer of the die. Although only twoorthogonal traces 54, 56 are illustrated, it should be appreciated thatany number of such traces may be situated below the differential lines50, 52. Orthogonal traces may also be present on a metal layer above thedifferential lines 50, 52. In the illustrated embodiment, the orthogonaltraces 54, 56 are coupled to a ground terminal 60 on the die. It shouldbe understood, however, that the orthogonal traces 54, 56 canalternatively be used as, for example, power and/or signal lines. Asdescribed above, in the illustrated embodiment, the traces 54, 56 areorthogonal to the differential signal lines 50, 52. In at least oneembodiment, however, the traces 54, 56 are at an oblique angle to thedifferential signal lines 50, 52 (i.e., they are neither orthogonal norparallel to the signal lines 50, 52).

In at least one application, the low loss interconnect structure of thepresent invention is used within a salphasic clock network. Salphasicclocking uses standing waves on a transmission medium to distribute aclock signal to multiple points within a system with relatively lowskew. Standing waves are created on a transmission line whenever asignal propagating on the transmission line encounters an impedancemismatch on the line. To purposely create a standing wave on atransmission line, an open or short circuit is typically used toterminate the line. When the transmission line is lossless, the standingwave will include a plurality of zero magnitude minima along the lengthof the transmission line that are located at half wavelength (i.e., λ/2)intervals. These minima mark the locations of abrupt 180 phase changesin the corresponding signal. In each region between adjacent minima, thephase of the corresponding signal is constant. Thus, to some extent, thephase of the signal has been made non-position dependent. It is thisnon-position dependent phase quality of the standing wave that is takenadvantage of in salphasic clocking.

FIG. 6 is a diagram illustrating a standing wave 70 that results when alossless transmission line is terminated in a short circuit. Asdescribed above, the standing wave 70 includes zero magnitude minima athalf wavelength intervals along the line. Because the termination is ashort circuit, a zero magnitude minima is also present at thetermination point (i.e., at x=0). As shown, the signal phase at allpoints between x=0 and x=λ/2 and between x=λ and x=3λ/2 is zero degrees.Similarly, the signal phase at all points between x=λ/2 and x=λ andbetween x=3λ/2 and x=2λ is 180 degrees. FIG. 7 is a diagram illustratinga standing wave 74 that results when a lossy transmission line isterminated in a short circuit. As shown, the minima of the standing wavepattern do not occur at zero magnitude as with the lossless line. Inaddition, an abrupt phase change is not achieved at half wavelengthintervals. Instead, a relatively wide region 76 exists at halfwavelength intervals where a gradual phase change between zero and 180degrees takes place. As can be appreciated, the presence of these largephase change regions 76 can significantly increase skew within acorresponding clock network. For this reason, low loss transmissionstructures are highly desired within salphasic clock networks.

As described previously, in the past, on-die interconnects weretypically relatively lossy structures. Thus, these structures were notoptimal for use in salphasic clocking networks. The interconnectstructure of the present invention, however, is capable of achievinglosses that are low enough to make on-die salphasic clocking feasible.In at least one embodiment, the effective loss of the low lossinterconnect structure is reduced even further by placing activeelements at various locations within the structure (e.g., at variouspoints within a grid) to provide signal gain. Negative impedanceconverter circuits can be used to reduce the skew proportionally to thedecrease in loss. The inventive interconnect structure can beimplemented in a variety of different salphasic clock distributionschemes, including salphasic tree structures (e.g., H trees and binarytrees) and salphasic grid structures.

FIG. 8 is a diagram illustrating a salphasic clock grid 80 that isimplemented on-die in accordance with one embodiment of the presentinvention. As illustrated, the salphasic clock grid 80 includes a numberof interconnect segments 82 that each include first and seconddifferential signal line portions 84, 86. The interconnect segments 82are connected together in a grid pattern that is used to distribute aclock signal to a number of loads (i.e., clocked elements) within acorresponding microelectronic device. The first differential signal lineportion 84 of each interconnect segment 82 is conductively coupled tothe first differential signal line portion 84 of each other interconnectsegment 82 of the grid 80 using conductive links 88. Similarly, thesecond differential signal line portion 86 of each interconnect segment82 is conductively coupled to the second differential signal lineportion 86 of each other interconnect segment 82 of the grid 80 usingconductive links 90. The conductive links 88, 90 will typically includetrace portions on other layers of the die (and corresponding viaconnections). As described previously, orthogonal traces may be presenton metal layers adjacent to the grid 80 to be used as, for example,power, ground, and/or signal lines.

In the illustrated embodiment, the salphasic clock grid 80 is fed adifferential clock signal at four different locations 92, 94, 96, 98 onthe grid 80. Buffer units having small signal, differential outputs canbe used to drive the grid 80 at these locations. The salphasic clockgrid 80 will generate standing waves using the differential clocksignal. The resulting standing wave pattern will depend on a number offactors including: the phasing of the four drive signals, the dimensionsof the grid 80, and the frequency of the clock signal. The standing wavepattern will have large regions where clock signal phase is positionindependent. Thus, the loads can be connected to the grid anywherewithin these regions to achieve low skew. In at least one embodiment,the signal phase is position independent for the entire grid 80. In apreferred approach, a sinusoidal clock signal is used to simplify phasedetection at the load locations, although other clock signal types canalternatively be used. As the reader will appreciate, the inventiveinterconnect structure can be implemented in a variety of other on-diesalphasic clock distribution structures.

Although the present invention has been described in conjunction withcertain embodiments, it is to be understood that modifications andvariations may be resorted to without departing from the spirit andscope of the invention as those skilled in the art readily understand.Such modifications and variations are considered to be within thepurview and scope of the invention and the appended claims.

1. A microelectronic die comprising: a clock signal source to provide aclock signal; and a clock signal distribution network to distribute saidclock signal to multiple clocked elements within said microelectronicdie using salphasic clocking techniques, said clock signal distributionnetwork including at least one on-die interconnect section comprisingfirst and second differential signal lines on a first metal layer ofsaid microelectronic die to carry a differential version of said clocksignal, said first and second differential signal lines beingsubstantially parallel to one another, wherein the first and seconddifferential signal lines each have widths such that the widths and aspacing between the first and second differential signal lines areselected to reduce inductance losses with a signal return path on asecond metal layer of said microelectronic die.
 2. The microelectronicdie of claim 1, comprising: at least one trace on the second metal layerof said microelectronic die, said at least one trace being capacitivelycoupled to and non-parallel with said first and second differentialsignal lines.
 3. The microelectronic die of claim 2, wherein: said atleast one trace is substantially orthogonal to said first and seconddifferential signal lines.
 4. The microelectronic die of claim 1,wherein: said clock signal is sinusoidal.
 5. The microelectronic die ofclaim 1, wherein: said first and second differential signal lines arepart of a clock grid within said clock distribution network.
 6. Themicroelectronic die of claim 1, wherein: said first and seconddifferential signal lines are part of an H-tree within said clockdistribution network.
 7. The microelectronic die of claim 1, whereinsaid microelectronic die includes microprocessor circuitry.
 8. Themicroelectronic die of claim 1, further including: additional number ofon-die interconnect sections, each of the additional on-die interconnectsections having first and second differential signal lines on the firstmetal layer of the microelectronic die to carry the differential versionof the clock signal, the first and second differential signal lines ofthe additional number of on-die interconnect sections beingsubstantially parallel to one another; and a number of conductive links,wherein a first conductive link of the number of conductive linkscouples the first differential signal line of a first one of theadditional interconnect sections to the first differential signal lineof a second one of the additional interconnect sections and a secondconductive link of the number of the conductive links couples the seconddifferential signal line of the first one of the additional interconnectsections to the second differential signal line of the second one of theadditional interconnect sections.
 9. The microelectronic die of claim 8,wherein said microelectronic die includes microprocessor circuitry. 10.The microelectronic die of claim 8, further including a number of traceson a second metal layer of the microelectronic die, the number of tracesbeing capacitively coupled to and non-parallel with the first and seconddifferential signal lines of the additional number of on-dieinterconnect sections.
 11. The microelectronic die of claim 10, whereinthe number of traces are substantially orthogonal to the first andsecond differential signal lines of the additional number of on-dieinterconnect sections.
 12. The microelectronic die of claim 10, whereinthe number of traces includes signal lines or power lines.
 13. Amicroelectronic die comprising: a clock signal source to provide a clocksignal; and a clock signal distribution network to distribute the clocksignal to multiple clocked elements within the microelectronic die usingsalphasic clocking techniques, the clock signal distribution networkincluding a number of on-die interconnect sections having first andsecond differential signal lines on a first metal layer of themicroelectronic die to carry a differential version of the clock signal,the first and second differential signal lines being substantiallyparallel to one another; and a number of conductive links, wherein afirst conductive link of the number of conductive links couples thefirst differential signal line of a first one of the interconnectsections to the first differential signal line of a second one of theinterconnect sections and a second conductive link of the number of theconductive links couples the second differential signal line of thefirst one of the interconnect sections to the second differential signalline of the second one of the interconnect sections, wherein themultiple clocked elements are coupled to the clock distribution networkat locations where the clock signal has a signal phase independent ofthe position of the locations.
 14. The microelectronic die of claim 13,wherein the clock signal distribution network includes a salphasic clockgrid in which the clock signal has a signal phase that is substantiallyposition independent for the entire salphasic clock grid.
 15. Themicroelectronic die of claim 13, further including a number of activeelements coupled to a number of points in the clock signal distributionnetwork to provide gain to the clock signal.
 16. The microelectronic dieof claim 13, wherein the microelectronic die is a microprocessor die.17. A microelectronic die comprising: a clock signal source to provide aclock signal; and a clock signal distribution network to distribute theclock signal to multiple clocked elements within the microelectronic dieusing salphasic clocking techniques, the clock signal distributionnetwork including an on-die interconnect section having first and seconddifferential signal lines on a first metal layer of the microelectronicdie to carry a differential version of the clock signal, the first andsecond differential signal lines, having a resistance per unit length,being substantially parallel to one another with a spacing between thefirst and second differential signal lines; and a number of traces on asecond metal layer of the microelectronic die, the number of tracesbeing capacitively coupled to and non-parallel with the first and seconddifferential signal lines providing a high inductance return path to theclock signal propagating on the first and second differential, the highinductance return path having an inductance per unit length, wherein awidth for each of the first and second differential signal lines and thespacing between the first and second differential signal lines areselected to decrease loss by decreasing a ratio of the resistance perunit length to the inductance per unit length.
 18. The microelectronicdie of claim 17, wherein the number of traces are substantiallyorthogonal to said first and second differential signal lines.
 19. Themicroelectronic die of claim 17, wherein the clock signal is sinusoidal.20. The microelectronic die of claim 17, wherein the first and seconddifferential signal lines are part of a clock grid within the clockdistribution network.
 21. The microelectronic die of claim 17, the firstand second differential signal lines are part of an H-tree within saidclock distribution network.
 22. The microelectronic die of claim 17,wherein the multiple clocked elements are coupled to the clockdistribution network at locations where the clock signal has a signalphase independent of the position of the locations.
 23. Themicroelectronic die of claim 17, wherein the clock signal distributionnetwork includes a salphasic clock grid in which the clock signal has asignal phase that is substantially position independent for the entiresalphasic clock grid.
 24. The microelectronic die of claim 17, furtherincluding a number of on-die interconnect sections having third andfourth differential signal lines and a number of conductive links,wherein a first conductive link of the number of conductive linkscouples the third differential signal line of a first one of theinterconnect sections to the third differential signal line of a secondone of the interconnect sections and a second conductive link of thenumber of the conductive links couples the fourth differential signalline of the first one of the interconnect sections to the fourthdifferential signal line of the second one of the interconnect sections.25. The microelectronic die of claim 17, wherein the clock signaldistribution network includes a salphasic clock grid having a number oflocations at which the clock signal is fed to the salphasic clock grid.26. The microelectronic die of claim 25, further including buffer unitsat the number of locations, the buffer units having small, differentialoutputs to drive the clock signal.
 27. The microelectronic die of claim25, wherein the salphasic clock grid provides the clock signal having asignal phase that is substantially position independent for the entiresalphasic clock grid.
 28. The microelectronic die of claim 25, whereinthe clock signal distribution network includes a salphasic clock grid inwhich the clock signal has a signal phase that is substantially positionindependent for the entire salphasic clock grid.